搜索资源列表
QIANGDA
- 基于FPGA的抢答器，verilog HDL 源码-FPGA-based Responder, verilog HDL source
LED-and-LCD-verilog-hdl
- 基于fpga开发电子时钟，显示用到led和lcd，总体设计思路-FPGA realization of research on the LCD display driver s control
FPGA-traffic-light
- 基于FPGA的交通灯控制器的设计，利用的是verilog HDL 语言。-design of traffic light based on FPGA,use the veriog HDL language.
fpga-uart
- 基于DE2开发板的串口通信程序，使用Verilog HDL语言，-Serial communication program based on the DE2 board, using the Verilog HDL language
UART
- FPGA串口通信程序，Verilog HDL语言下的UART串口通信程序-Verilog HDL UART
ADDALOOP
- verilog HDL相关的学习资料，对于FPGA与Verilog HDL的初学者有很大帮助。-verilog HDL learning materials for FPGA Verilog HDL beginners.
digital-frequency-counter
- 基于FPGA的数字频率计，verilog hdl编写-digital frequency counter ，using verilog hdl
shu_ma
- 基于fpga的数码管实验，用verilog hdl编写，-Verilog hdl fpga-based digital tube experiments, write,
fpga-draw
- 二维图形加速器设计与实现。采用Verilog HDL语言对各功能模块进行了设计,包括画线、画圆、画椭圆、多边形填充以及区域复制等,总结了一套将算法使用硬件描述语言实现的一般流程.这是本人花了50大洋买的，吐血奉献-Design and implementation of a two-dimensional graphics accelerator. Using Verilog HDL language of each functional module design, draw lines, d
fpga
- 这是一个利用verilog HDL语言编写的自动频率计设计项目，能运行-This is a verilog HDL language automatic frequency meter design projects, and be able to run
FIFO
- 三种同步方式实现的FIFO，verilog HDL，FPGA，更好理解FIFO-The three implemented synchronously FIFO, Verilog HDL, FPGA, a better understanding of the FIFO
DE2-70
- DE2-70 FPGA开发板学习实例及代码，Verilog HDL-DE2-70 FPGA development board learning examples and code, Verilog HDL
motor_basic
- 基于FPGA的直流电机闭环控制，Verilog HDL编写的源代码-DC motor closed-loop control based on FPGA, Verilog source code written in HDL DC motor closed-loop control based on FPGA, the Verilog HDL source code
zhu
- 基于FPGA的SPI接口设计，主模式，频率可调，verilog HDL编写-FPGA-based SPI interface design, master mode, adjustable frequency, verilog HDL prepared
verilog-hdl
- 很少有完整介绍ISE环境下FPGA开发的资料，这是在Xilinx ISE开发平台下进行FPGA设计比较好的教程，感觉挺不错的-there is few full descr iption ISE FPGA development environment information, which is in the Xilinx ISE development platform for FPGA design is a good tutorial, I feel pretty good
clock_gating
- 在FPGA里运用Verilog HDL编写实现门控时钟，而不产生毛刺-In the FPGA using Verilog HDL prepared to achieve clock gating, without glitches
chaoche
- 基于FPGA的Verilog HDL编写的黑线控制小车直线，及检测黑线延迟减速的设计。-FPGA-based Verilog HDL prepared to control the car straight black lines, and testing the black wire delay reducer design.
mux4booth
- fpga 使用verilog hdl 语言，quartusii 9.0编程环境，使用2booth算法设计的4bit乘法器。可以扩展为16bit乘法器。-fpga verilog hdl ，quartusii 9.0 ，2booth 4bit
top_module
- fpga 使用verilog hdl 语言，quartusii 9.0编程环境，设计的4个led灯分别实现不同功能，然后由一个顶层文件调用，完成总的设计。-fpga using verilog hdl language, quartusii 9.0 programming environment designed four different functions, respectively, led lights, followed by a top-level document called,
C6474L_EVM_RTL
- TI C6474评估板的fpga源代码，初始化板子必备代码，Verilog HDL硬件语言编写。-TI C6474 evaluation board fpga source code, the code necessary to initialize the board, Verilog HDL hardware language.